вЂњWe see a reduction of up to 300 mW per port when the port is fully utilized,вЂќ Edlis said. The reduction of lanes, along with their associated components such as the buffers, reduces the overall power consumption of the system. So now there is a total of just eight lanes operating at 20 GT/s instead of seventeen lanes operating at 8 GT/s. Instead of the seventeen PCIe lanes from the prior generation, Ice Lake exposes just eight lanes вЂ“ four lanes to each retimer which drive the signals to the connectors. The biggest change comes from the fact that most of the Titan Ridge logic has been integrated into the Ice Lake SoC itself, reducing board space, routing, and the overall bill of materials. The simplification manifests itself in a number of ways. With Ice Lake, the circuit has been simplified a fair amount. The diagram below shows just one of those sides, using a dual-port controller. All in all, the Titan Ridge controller alone required a total of seventeen lanes operating at around 8 GT/s.Д«y the way, due to the complexity involved, most devices today only have the Thunderbolt 3 ports on that one side with the Titan Ridge controller. For charging capabilities, the port was also connected directly to a Power Deliver (PD) controller. In order to offer legacy I/O support, a direct USB 2.0 link from the PCH went to the port.

Each of those passed over four PCIe Gen 3 lanes. The chipset was connected over four PCIe Gen 3 lanes. In this configuration, Titan Ridge was connected to both the CPU itself and the chipset. Titan Ridge comes with support for either one or two dedicated Tb3 ports.

This is a discrete Thunderbolt 3 chip designed by Intel. In existing 8th Generation processors, in order to provide Thunderbolt 3 capabilities, OEMs have to use the Titan Ridge controller. Thunderbolt 3 Integration вЂ“ Outside Ice Lake Intel considers USB 4 a spec-driven approach whereas Thunderbolt remains a holistic solution which includes validation, verification, and comes with certain guarantees. Intel says that it believes Ice Lake is actually already USB 4-compliant, however, it cannot certify their source side as compliant until the sync side is made available for testing. The move was an effort by Intel to accelerate the adoption of Thunderbolt 3. In other words, the total bandwidth can be dynamically allocated on-demand depending on the kind of peripherals currently being connected and on the behavior of the currently running workload.Д®arlier this year, Intel contributed the Thunderbolt 3 protocol to USB 4. Through a quality of service mechanism, the device can decide which protocol, either DP or PCIe, gets what kind of priority. The key feature of TB3 is dynamic allocation. ItвЂ™s a single interface that combines all the protocols we listed above. Thunderbolt is a tunneling-based architecture.

8th gen intel thunderbolt 3